The subject matter relates to a semiconductor design technology, and more particularly, to a write path of a synchronous semiconductor memory device.
Semiconductor memory devices, such as a dynamic random access memory (DRAM), receive write data from a chipset (a memory controller), and transfer read data to the chipset. Meanwhile, synchronous semiconductor memory devices operate in synchronization with a system clock. However, when transferring data from the chipset to the memory device, skew occurs between data and a system clock due to different loading and traces for data and the system clock and location differences between the system clock and a plurality of memory devices.
In order to reduce the skew between the data and the system clock, a data strobe signal (DQS) is transferred together with data when transferring the data from the chipset to the memory device. The data strobe signal (DQS) is also called an echo clock. By strobing the data using the data strobe signal (DQS), skew occurring due to the location difference between the system clock and the memory devices can be reduced because the data strobe signal (DQS) has the same loading and trace as the data. Meanwhile, in a read operation, the memory device transfers a read data strobe signal (DQS) to the chipset together with the data.
FIG. 1 is a circuit diagram illustrating a write path of a conventional synchronous semiconductor memory device.
Referring to FIG. 1, on the write path, the conventional synchronous semiconductor memory device includes a DQS input buffer unit 110, a data strobe falling pulse (DSFP) generating unit 120, a DQS buffer disable signal generating unit 130, a data alignment unit 140, and a global data line (GDL) write driving unit 150. The DQS input buffer unit 110 buffers a data strobe signal DQS in response to a DQS buffer disable signal DISABLE_DQS. The DSFP generating unit 120 receives an output signal of the DQS input buffer unit 110 to generate a data strobe falling pulse DSFP in synchronization with a falling edge of the data strobe signal DQS. The DQS buffer disable signal generating unit 130 generates the DQS buffer disable signal DISABLE_DQS in response to the data strobe falling pulse DSFP, a data strobe disable signal DIS_DSP, and a write pulse WTPb. The data strobe disable signal DIS_DSP is a signal that is pulsed to a logic high level after a time corresponding to a burst length (BL) elapses from the input of a write command, and the write pulse WTPb is a signal that is pulsed to a logic low level when a write command is input. The data alignment unit 140 aligns input data DIN in response to the data strobe falling pulse DSFP. The input data DIN are data output from a data input buffer (not shown). The GDL write driving unit 150 transfers the aligned data ALGN_R0, ALGN_R1, ALGN_F0 and ALGN_F1 output from the data alignment unit 140 through global data lines GDL_Q0, GDL_Q1, GDL_Q2 and GDL_Q3 in synchronization with a data input clock DINCLK. The data input clock DINCLK is a signal that is pulsed to a logic high level after a predetermined time considering a write latency (WL) elapses from the input of the write command.
The DQS buffer disable signal generating unit 130 includes an AND gate AND1, a pull-up PMOS transistor MP1, a pull-down NMOS transistor MN1, and a latch INV1 and INV2. The AND gate AND1 performs an AND operation on the data strobe falling pulse DSFP and the data strobe disable signal DIS_DSP. The pull-up PMOS transistor MP1 has a source connected to a power supply voltage terminal VDD, a drain connected to a DISABLE_DQS output terminal N1, and a gate receiving the write pulse WTPb. The pull-down NMOS transistor MN1 has a source connected to a ground voltage terminal VSS, a drain connected to the DISABLE_DQS output terminal N1, and a gate receiving an output signal of the AND gate AND1. The latch INV1 and INV2 latches a signal applied to the DISABLE_DQS output terminal N1.
The data alignment unit 140 includes an inverter INV3, a D flip-flop 142, a D flip-flop 144, a D flip-flop 146, and a D flip-flop 148. The inverter INV3 inverts the data strobe falling pulse DSFP, and the D flip-flop 142 transfers the input data DIN in response to a falling edge of an output signal of the inverter INV3. The D flip-flop 144 transfers the aligned data ALGN_R1 output from the D flip-flop 142 in response to the falling edge of the output signal of the inverter INV3. The D flip-flop 146 transfers the input data DIN in response to the falling edge of the output signal of the inverter INV3. The D flip-flop 148 transfers the aligned data ALGN_F1 output from the D flip-flop 146 in response to the falling edge of the output signal of the inverter INV3.
The GDL write driving unit 150 includes GDL write drivers 152, 154, 156 and 158. The GDL write driver 152 transfers the aligned data ALGN_R0 output from the D flip-flop 144 to the global data line GDL_Q0 in synchronization with the data input clock DINCLK. The GDL write driver 154 transfers the aligned data ALGN_R1 output from the D flip-flop 142 to the global data line GDL_Q1 in synchronization with the data input clock DINCLK. The GDL write driver 156 transfers the aligned data ALGN_F0 output from the D flip-flop 148 to the global data line GDL_Q2 in synchronization with the data input clock DINCLK. The GDL write driver 158 transfers the aligned data ALGN_F1 output from the D flip-flop 146 to the global data line GDL_Q3 in synchronization with the data input clock DINCLK.
FIG. 2 is a timing diagram of the conventional synchronous semiconductor memory device of FIG. 1.
Referring to FIG. 2, when the write command is input, the memory device receives the data DQ together with the data strobe signal DQS. In FIG. 2, a burst write command is input (BL=4) and a reference symbol “INT_WT” represents an internal write command signal.
The DSFP generating unit 120 generates the data strobe falling pulse DSFP that is activated to a logic high level at each falling edge of the data strobe signal DQS, and the data alignment unit 140 outputs the aligned data ALGN_R0, ALGN_R1, ALGN_F0 and ALGN_F1 in synchronization with rising edges of the data strobe signal DSFP.
When the input of the data DQ is completed and thus both the data strobe falling pulse DSFP and the data strobe disable signal DIS_DSP become a logic high level, the DQS buffer disable signal generating unit 130 changes the DQS buffer disable signal DISABLE_DQS to a logic low level. Thus, the DQS input buffer unit 110 is disabled so that it does not receive the data strobe signal DQS any more.
The GDL write drivers 152, 154, 156 and 158 transfer the aligned data ALGN_R0, ALGN_R1, ALGN_F0 and ALGN_F1 to the global data lines GDL_Q0, GDL_Q1, GDL_Q2 and GDL_Q3 in synchronization with the data input clock DINCLK.
However, when the toggling data strobe signal DQS returns to a high impedance (Hi-Z) after the last falling edge, one-time ringing often occurs. This phenomenon is called a write postamble ringing.
FIG. 3 is a timing diagram of the synchronous semiconductor memory device of FIG. 1 when a write postamble ringing occurs.
It can be seen from FIG. 3 that the ringing occurs when the toggling data strobe signal DQS returns to the high impedance (Hi-Z).
If the ringing occurs before the DQS buffer enable signal DISABLE_DQS changes to a logic low level, the DSFP generating unit 120 recognizes it as the falling edge of the data strobe signal DQS, so that glitch is generated at the data strobe falling pulse DSFP.
Due to the glitch, the values of the aligned data ALGN_R0, ALGN_R1, ALGN_F0 and ALGN_F1 are early changed. Therefore, incorrect data are input at the rising edges of the data input clock DINCLK, and undesired data are loaded on the global data lines GDL_Q0, GDL_Q1, GDL_R2 and GDL_Q3.
Such problems may occur when the write command is independently applied, as well as when the write command is successively input.